Transaction level models analyzer in PROLOG

Andrzej Pułka

doi:10.1016/S1474-6670(17)30611-0

Transaction level models analyzer in PROLOG

Andrzej Pułka

Katedra Elektroniki, Elektrotechniki i Mikroelektroniki (RAU/RAU11)

Wyniki badań: Wkład do czasopisma › Artykuł z konferencji › recenzja

2 Cytowania z bazy Scopus

Abstrakt

Paper deals with a new design methodology in the domain of Systems on Chip (SoC) based on systems modeling in SystemC. Transaction Level Models (TLMs) have been introduced in the system-level design tools recently. In this contribution the author presents an approach to the problem of concurrent (hardware-software) electronics embedded systems design. A system partitioning based on the Transaction Level Models analysis implemented in PROLOG is presented. Some issues concerning system partitioning into software and hardware components are outlined. Conclusions and obtained results are discussed.

Język oryginału	angielski
Strony (od–do)	278-283
Liczba stron	6
Czasopismo	IFAC-PapersOnLine
Tom	37
Numer wydania	20
Identyfikatory DOI	https://doi.org/10.1016/S1474-6670(17)30611-0
Status publikacji	Opublikowano - 2004
Wydarzenie	2004 IFAC Workshop on Programmable Devices and Systems, PDS 2004 - Cracow, Polska Czas trwania: 18 lis 2004 → 19 lis 2004

Obszary tematyczne ASJC Scopus

Inżynieria sterowania i systemów

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10.1016/S1474-6670(17)30611-0

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@article{68643898b6034f32b783d81452eea914,

title = "Transaction level models analyzer in PROLOG",

abstract = "Paper deals with a new design methodology in the domain of Systems on Chip (SoC) based on systems modeling in SystemC. Transaction Level Models (TLMs) have been introduced in the system-level design tools recently. In this contribution the author presents an approach to the problem of concurrent (hardware-software) electronics embedded systems design. A system partitioning based on the Transaction Level Models analysis implemented in PROLOG is presented. Some issues concerning system partitioning into software and hardware components are outlined. Conclusions and obtained results are discussed.",

keywords = "Architectures, Components, Decomposition, Design VLSI, Embedded systems, Hardware, Models, Optimization, Systems design",

author = "Andrzej Pu{\l}ka",

note = "Publisher Copyright: {\textcopyright} 2004 IFAC.; 2004 IFAC Workshop on Programmable Devices and Systems, PDS 2004 ; Conference date: 18-11-2004 Through 19-11-2004",

year = "2004",

doi = "10.1016/S1474-6670(17)30611-0",

language = "English",

volume = "37",

pages = "278--283",

journal = "IFAC-PapersOnLine",

issn = "2405-8971",

publisher = "Elsevier B.V.",

number = "20",

}

TY - JOUR

T1 - Transaction level models analyzer in PROLOG

AU - Pułka, Andrzej

PY - 2004

Y1 - 2004

N2 - Paper deals with a new design methodology in the domain of Systems on Chip (SoC) based on systems modeling in SystemC. Transaction Level Models (TLMs) have been introduced in the system-level design tools recently. In this contribution the author presents an approach to the problem of concurrent (hardware-software) electronics embedded systems design. A system partitioning based on the Transaction Level Models analysis implemented in PROLOG is presented. Some issues concerning system partitioning into software and hardware components are outlined. Conclusions and obtained results are discussed.

AB - Paper deals with a new design methodology in the domain of Systems on Chip (SoC) based on systems modeling in SystemC. Transaction Level Models (TLMs) have been introduced in the system-level design tools recently. In this contribution the author presents an approach to the problem of concurrent (hardware-software) electronics embedded systems design. A system partitioning based on the Transaction Level Models analysis implemented in PROLOG is presented. Some issues concerning system partitioning into software and hardware components are outlined. Conclusions and obtained results are discussed.

KW - Architectures

KW - Components

KW - Decomposition

KW - Design VLSI

KW - Embedded systems

KW - Hardware

KW - Models

KW - Optimization

KW - Systems design

UR - https://www.scopus.com/pages/publications/34547279701

U2 - 10.1016/S1474-6670(17)30611-0

DO - 10.1016/S1474-6670(17)30611-0

M3 - Conference article

AN - SCOPUS:34547279701

SN - 2405-8971

VL - 37

SP - 278

EP - 283

JO - IFAC-PapersOnLine

JF - IFAC-PapersOnLine

IS - 20

T2 - 2004 IFAC Workshop on Programmable Devices and Systems, PDS 2004

Y2 - 18 November 2004 through 19 November 2004

ER -

Transaction level models analyzer in PROLOG

Abstrakt

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