Tolerance maximisation in fault diagnosis of analogue electronic circuits

Łukasz Chruszczyk; Jerzy Rutkowski

Tolerance maximisation in fault diagnosis of analogue electronic circuits

Przetłumaczony tytuł wkładu: Maksymalizacja tolerancji w diagnostyce uszkodzeń analogowych układów elektronicznych

Łukasz Chruszczyk
, Jerzy Rutkowski

Katedra Elektroniki, Elektrotechniki i Mikroelektroniki (RAU/RAU11)

Silesian University of Technology

Wyniki badań: Wkład do czasopisma › Artykuł › recenzja

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Abstrakt

This paper presents method of designing periodic test excitation for fault diagnosis of analogue electronic circuits. There has been proposed maximisation of circuit components tolerances while keeping assumed level of fault diagnosis. There has also been shown that combination of fault detection and location in a single step can remarkably shorten testing time. The optimisation process involves genetic algorithm.

Przetłumaczony tytuł wkładu	Maksymalizacja tolerancji w diagnostyce uszkodzeń analogowych układów elektronicznych
Język oryginału	angielski
Strony (od–do)	159-163
Liczba stron	5
Czasopismo	Przeglad Elektrotechniczny
Tom	87
Numer wydania	10
Status publikacji	Opublikowano - 2011

Obszary tematyczne ASJC Scopus

Inżynieria elektryczna i elektroniczna

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Cytowanie

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title = "Tolerance maximisation in fault diagnosis of analogue electronic circuits",

abstract = "This paper presents method of designing periodic test excitation for fault diagnosis of analogue electronic circuits. There has been proposed maximisation of circuit components tolerances while keeping assumed level of fault diagnosis. There has also been shown that combination of fault detection and location in a single step can remarkably shorten testing time. The optimisation process involves genetic algorithm.",

keywords = "Analogue electronics, Components tolerance, Fault diagnosis, Genetic algorithm, Test time reduction",

author = "{\L}ukasz Chruszczyk and Jerzy Rutkowski",

year = "2011",

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AU - Rutkowski, Jerzy

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AB - This paper presents method of designing periodic test excitation for fault diagnosis of analogue electronic circuits. There has been proposed maximisation of circuit components tolerances while keeping assumed level of fault diagnosis. There has also been shown that combination of fault detection and location in a single step can remarkably shorten testing time. The optimisation process involves genetic algorithm.

KW - Analogue electronics

KW - Components tolerance

KW - Fault diagnosis

KW - Genetic algorithm

KW - Test time reduction

UR - https://www.scopus.com/pages/publications/81155139186

M3 - Article

AN - SCOPUS:81155139186

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JO - Przeglad Elektrotechniczny

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Tolerance maximisation in fault diagnosis of analogue electronic circuits

Abstrakt

Obszary tematyczne ASJC Scopus

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Cytowanie