Abstrakt
This paper presents an analysis of an influence of global parametric faults (GPF) on analogue integrated circuits (AIC) time domain (TD) response features, such as overshoot, delay time, rise time, maxima and minima, first differential maxima and minima. The novel approach is the analysis of relations and superrelations between features which are discussed in details. The presented results should increase testability and diagnosability of the global parametric faults on a production line of analogue and mixed electronic circuits. The recently observed AIC faults belong to parametric ones and are caused by technological process. GPF influence on aforementioned features is presented with the use of an exemplary circuit. A research presented in this paper may be used as an introduction to a Fault Driven Test (FDT) diagnosis with the use of Simulation Before Test (SBT) methods.
| Język oryginału | angielski |
|---|---|
| Strony | 299-303 |
| Liczba stron | 5 |
| Identyfikatory DOI | |
| Status publikacji | Opublikowano - 2008 |
| Wydarzenie | 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS - Bratislava, Słowacja Czas trwania: 16 kwi 2008 → 18 kwi 2008 |
Konferencja
| Konferencja | 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS |
|---|---|
| Kraj/Terytorium | Słowacja |
| Miejscowość | Bratislava |
| Okres | 16/04/08 → 18/04/08 |
Obszary tematyczne ASJC Scopus
- Inżynieria elektryczna i elektroniczna
- Inżynieria sterowania i systemów
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