Abstrakt
The need to apply the test-per-clock method at full clock rates to test crosstalks in networks of long interconnects between modules in a System on a Chip (SoC) is highlighted. Our method involves the 3n-R-LFSR (Ring Linear Feedback Shift Register). The part of the R-LFSR that generates test patterns for n-interconnects has double number of flip-flops where every second flip-flop is connected to the network of Interconnects Under Test (IUT). It has been proved that the 3n-R-LFSR is capable to generate all the two-test patterns that are necessary for IUT. The completed simulation experiments evidenced efficiency of the method application to test crosstalks that are manifested by either a glitch or an edge delay.
| Język oryginału | angielski |
|---|---|
| Strony (od–do) | 133-137 |
| Liczba stron | 5 |
| Czasopismo | Przeglad Elektrotechniczny |
| Tom | 86 |
| Numer wydania | 11 A |
| Status publikacji | Opublikowano - 2010 |
Obszary tematyczne ASJC Scopus
- Inżynieria elektryczna i elektroniczna
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