Non-binary LDPC Decoders Design for Maximizing Throughput of an FPGA Implementation

Most of the recently proposed hardware realizations for non-binary low-density parity-check decoders are ASIC oriented as they employ multiplierless computation units. In this article, we present a different decoder design approach that is specifically intended for an FPGA implementation. We reformulate the mixed-domain FFT-BP decoding algorithm and develop a decoder architecture that does not exclude the multiplication units. This allows mapping a part of the algorithm to the multiplier cores embedded in an FPGA, thus making use of all the types of FPGA resources. Then, the throughput limit achievable in a single FPGA by the proposed decoder is significantly increased. We also consider another important optimization of the decoder implementation, mainly an efficient realization of the permutation units and an approximated evaluation of the nonlinear functions of messages. Another motivation is to make the decoder easily scalable for FPGA devices of different sizes. To achieve this goal, the configurable semi-parallel decoder architecture is applied operating for the structured subclass of codes.