@inproceedings{7c66d0fcb8f24ee3943e4a098733a24d,
title = "JumpSAT Based System Verification Scenarios",
abstract = "The paper presents a methodology of formal verification based on SAT solving technique. The author briefly recalls the JumpSAT algorithm. Then various aspects of the formal verification are presented and different approaches to the system level formal verification based on the JumpSAT algorithm are discussed on examples. Conclusions concerning the presented approach are given.",
keywords = "Formal verification, SAT solving, SAT-based verification, System level modeling",
author = "Andrzej Pulka",
note = "Publisher Copyright: {\textcopyright} 2018 IEEE.; 10th International Conference on Signals and Electronic Systems, ICSES 2018 ; Conference date: 10-09-2018 Through 12-09-2018",
year = "2018",
month = oct,
day = "24",
doi = "10.1109/ICSES.2018.8507290",
language = "English",
series = "2018 International Conference on Signals and Electronic Systems, ICSES 2018 - Proceedings",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
pages = "301--306",
editor = "Jacek Stepien and Witold Machowski",
booktitle = "2018 International Conference on Signals and Electronic Systems, ICSES 2018 - Proceedings",
address = "United States",
}