Hardware implementation of a control program in FPGA structures

Jan Mocha; Dariusz Kania

Hardware implementation of a control program in FPGA structures

Przetłumaczony tytuł wkładu: Sprzętowa realizacja programu sterowania w strukturach FPGA

Katedra Systemów Cyfrowych (RAU/RAU12)

Wyniki badań: Wkład do czasopisma › Artykuł › recenzja

29 Cytowania z bazy Scopus

Abstrakt

The paper presents an original method of implementing control programs, represented in Ladder Diagram (LD) format, in Programmable Logic Devices. The essence of the solution proposed in the paper consists in an original algorithm of extracting events that have to be processed sequentially, or can be processed concurrently. For this purpose a Network Ordered Graph is used. The graph is a link between a control algorithm described in Ladder Diagram, and the same algorithm described in Hardware Description Language (HDL).

Przetłumaczony tytuł wkładu	Sprzętowa realizacja programu sterowania w strukturach FPGA
Język oryginału	angielski
Strony (od–do)	95-100
Liczba stron	6
Czasopismo	Przeglad Elektrotechniczny
Tom	88
Numer wydania	12 A
Status publikacji	Opublikowano - 2012

Obszary tematyczne ASJC Scopus

Inżynieria elektryczna i elektroniczna

Inne pliki i linki

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Cytowanie

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title = "Hardware implementation of a control program in FPGA structures",

abstract = "The paper presents an original method of implementing control programs, represented in Ladder Diagram (LD) format, in Programmable Logic Devices. The essence of the solution proposed in the paper consists in an original algorithm of extracting events that have to be processed sequentially, or can be processed concurrently. For this purpose a Network Ordered Graph is used. The graph is a link between a control algorithm described in Ladder Diagram, and the same algorithm described in Hardware Description Language (HDL).",

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author = "Jan Mocha and Dariusz Kania",

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language = "English",

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pages = "95--100",

journal = "Przeglad Elektrotechniczny",

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AU - Kania, Dariusz

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AB - The paper presents an original method of implementing control programs, represented in Ladder Diagram (LD) format, in Programmable Logic Devices. The essence of the solution proposed in the paper consists in an original algorithm of extracting events that have to be processed sequentially, or can be processed concurrently. For this purpose a Network Ordered Graph is used. The graph is a link between a control algorithm described in Ladder Diagram, and the same algorithm described in Hardware Description Language (HDL).

KW - FPGA

KW - Hardware control program realisation

KW - Ladder diagram

KW - Programmable logic controller

KW - Programmable logic device

UR - https://www.scopus.com/pages/publications/84870657845

M3 - Article

AN - SCOPUS:84870657845

SN - 0033-2097

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JO - Przeglad Elektrotechniczny

JF - Przeglad Elektrotechniczny

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ER -

Hardware implementation of a control program in FPGA structures

Abstrakt

Obszary tematyczne ASJC Scopus

Inne pliki i linki

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Cytowanie