@inbook{154520badb744694982dce76147c0769,
title = "Efficient technology mapping method for PAL-based devices",
abstract = "The core of a contemporary CPLD device is a PAL-based logic block which consists of a programmable AND matrix and a fixed OR matrix. A new technology mapping method for PAL-based devices based on the analysis of graph of outputs is described. The presented approach uses original method for illustrating a minimized form of a multi-output Boolean function. Graph node represents groups of multiple-output implicants with common output part. The essence of the method is the process of searching for appropriate multi-output implicants that can be shared by several functions. A new method for the description of cascaded feedback connections is presented. The experimental results show that the proposed algorithm leads to significant reduction of chip area used by resulting circuits.",
author = "Dariusz Kania",
year = "2011",
doi = "10.1007/978-3-642-17545-9\_6",
language = "English",
isbn = "9783642175442",
series = "Lecture Notes in Electrical Engineering",
pages = "145--163",
editor = "Marian Adamski and Alexander Barkalov and Marek Wegrzyn",
booktitle = "Design of Digital Systems and Devices",
}