Central processing units for PLC implementation in Virtex-4 FPGA

The paper presents an approach to the design and construction of central processing units for programmable logic controllers implemented in a FPGA development platform. Presented units are optimised for minimum response- and throughput time. The CPU structure is based on bit-word architecture and two types of control data exchange methods: with handshaking - control data are passed through the two flip-flop units with acknowledgement; without handshaking - control data are passed through the dual port RAM. Third unit - simple one processor - built to compare with the above two. The paper presents specific timers/counters hardware construction solution. Additionally it presents implementation results which show how many FPGA circuit resources are used to implement presented units.