Weryfikacja mocy strat w obwodzie bramkowym wybranych tranzystorów MOSFET na bazie Si i SiC

Krzysztof Przybyła

doi:10.15199/48.2018.01.33

Weryfikacja mocy strat w obwodzie bramkowym wybranych tranzystorów MOSFET na bazie Si i SiC

Translated title of the contribution: Verification of power losses in the gate circuit in selected MOSFET transistors based on Si and SiC

Krzysztof Przybyła

Department of Power Electronics, Electrical Drives and Robotics (RE/RE5)

Research output: Contribution to journal › Article › peer-review

Abstract

Measurement results of power losses in the gate circuit in Si: APT5010JFLL, IXFN44N80P and SiC: APT40SM120J MOSFET transistors are presented in the paper. Measurements were taken in class DE inverter configuration in frequency range from 275 kHz to 525 kHz and with inverter supply voltage E=0 V and E=300 V. The article contains also the comparison of evaluated power loss values, based on datasheets, with laboratory results.

Translated title of the contribution	Verification of power losses in the gate circuit in selected MOSFET transistors based on Si and SiC
Original language	Polish
Pages (from-to)	129-132
Number of pages	4
Journal	Przeglad Elektrotechniczny
Volume	21
Issue number	2
DOIs	https://doi.org/10.15199/48.2018.01.33
Publication status	Published - 2018

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.15199/48.2018.01.33

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@article{df2bf925b057472cbafc7e39ae2feb20,

title = "Weryfikacja mocy strat w obwodzie bramkowym wybranych tranzystor{\'o}w MOSFET na bazie Si i SiC",

abstract = "Measurement results of power losses in the gate circuit in Si: APT5010JFLL, IXFN44N80P and SiC: APT40SM120J MOSFET transistors are presented in the paper. Measurements were taken in class DE inverter configuration in frequency range from 275 kHz to 525 kHz and with inverter supply voltage E=0 V and E=300 V. The article contains also the comparison of evaluated power loss values, based on datasheets, with laboratory results.",

keywords = "Gate circuit, MOSFET, Power losses, SiC",

author = "Krzysztof Przyby{\l}a",

year = "2018",

doi = "10.15199/48.2018.01.33",

language = "polski",

volume = "21",

pages = "129--132",

journal = "Przeglad Elektrotechniczny",

issn = "0033-2097",

publisher = "Wydawnictwo SIGMA-NOT",

number = "2",

}

TY - JOUR

T1 - Weryfikacja mocy strat w obwodzie bramkowym wybranych tranzystorów MOSFET na bazie Si i SiC

AU - Przybyła, Krzysztof

PY - 2018

Y1 - 2018

N2 - Measurement results of power losses in the gate circuit in Si: APT5010JFLL, IXFN44N80P and SiC: APT40SM120J MOSFET transistors are presented in the paper. Measurements were taken in class DE inverter configuration in frequency range from 275 kHz to 525 kHz and with inverter supply voltage E=0 V and E=300 V. The article contains also the comparison of evaluated power loss values, based on datasheets, with laboratory results.

AB - Measurement results of power losses in the gate circuit in Si: APT5010JFLL, IXFN44N80P and SiC: APT40SM120J MOSFET transistors are presented in the paper. Measurements were taken in class DE inverter configuration in frequency range from 275 kHz to 525 kHz and with inverter supply voltage E=0 V and E=300 V. The article contains also the comparison of evaluated power loss values, based on datasheets, with laboratory results.

KW - Gate circuit

KW - MOSFET

KW - Power losses

KW - SiC

UR - https://www.scopus.com/pages/publications/85116475231

U2 - 10.15199/48.2018.01.33

DO - 10.15199/48.2018.01.33

M3 - Artykuł

AN - SCOPUS:85116475231

SN - 0033-2097

VL - 21

SP - 129

EP - 132

JO - Przeglad Elektrotechniczny

JF - Przeglad Elektrotechniczny

IS - 2

ER -

Weryfikacja mocy strat w obwodzie bramkowym wybranych tranzystorów MOSFET na bazie Si i SiC

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