Tolerance maximisation in fault diagnosis of analogue electronic circuits

Łukasz Chruszczyk; Jerzy Rutkowski

Tolerance maximisation in fault diagnosis of analogue electronic circuits

Łukasz Chruszczyk
, Jerzy Rutkowski

Department of Electronics; Electrical Engineering and Microelectronics (RAU/RAU11)

Silesian University of Technology

Research output: Contribution to journal › Article › peer-review

1 Citation (Scopus)

Abstract

This paper presents method of designing periodic test excitation for fault diagnosis of analogue electronic circuits. There has been proposed maximisation of circuit components tolerances while keeping assumed level of fault diagnosis. There has also been shown that combination of fault detection and location in a single step can remarkably shorten testing time. The optimisation process involves genetic algorithm.

Translated title of the contribution	Maksymalizacja tolerancji w diagnostyce uszkodzeń analogowych układów elektronicznych
Original language	English
Pages (from-to)	159-163
Number of pages	5
Journal	Przeglad Elektrotechniczny
Volume	87
Issue number	10
Publication status	Published - 2011

Keywords

Analogue electronics
Components tolerance
Fault diagnosis
Genetic algorithm
Test time reduction

ASJC Scopus subject areas

Electrical and Electronic Engineering

Cite this

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title = "Tolerance maximisation in fault diagnosis of analogue electronic circuits",

abstract = "This paper presents method of designing periodic test excitation for fault diagnosis of analogue electronic circuits. There has been proposed maximisation of circuit components tolerances while keeping assumed level of fault diagnosis. There has also been shown that combination of fault detection and location in a single step can remarkably shorten testing time. The optimisation process involves genetic algorithm.",

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AU - Rutkowski, Jerzy

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AB - This paper presents method of designing periodic test excitation for fault diagnosis of analogue electronic circuits. There has been proposed maximisation of circuit components tolerances while keeping assumed level of fault diagnosis. There has also been shown that combination of fault detection and location in a single step can remarkably shorten testing time. The optimisation process involves genetic algorithm.

KW - Analogue electronics

KW - Components tolerance

KW - Fault diagnosis

KW - Genetic algorithm

KW - Test time reduction

UR - https://www.scopus.com/pages/publications/81155139186

M3 - Article

AN - SCOPUS:81155139186

SN - 0033-2097

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JO - Przeglad Elektrotechniczny

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IS - 10

ER -

Tolerance maximisation in fault diagnosis of analogue electronic circuits

Abstract

Keywords

ASJC Scopus subject areas

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