The influence of global parametric faults on analogue electronic circuits time domain response features

P. Jantos; D. Grzechca; T. Golonek; J. Rutkowski

doi:10.1109/DDECS.2008.4538806

The influence of global parametric faults on analogue electronic circuits time domain response features

P. Jantos
, D. Grzechca
, T. Golonek
, J. Rutkowski

Department of Electronics; Electrical Engineering and Microelectronics (RAU/RAU11)

Silesian University of Technology

Research output: Contribution to conference › Paper › peer-review

9 Citations (Scopus)

Abstract

This paper presents an analysis of an influence of global parametric faults (GPF) on analogue integrated circuits (AIC) time domain (TD) response features, such as overshoot, delay time, rise time, maxima and minima, first differential maxima and minima. The novel approach is the analysis of relations and superrelations between features which are discussed in details. The presented results should increase testability and diagnosability of the global parametric faults on a production line of analogue and mixed electronic circuits. The recently observed AIC faults belong to parametric ones and are caused by technological process. GPF influence on aforementioned features is presented with the use of an exemplary circuit. A research presented in this paper may be used as an introduction to a Fault Driven Test (FDT) diagnosis with the use of Simulation Before Test (SBT) methods.

Original language	English
Pages	299-303
Number of pages	5
DOIs	https://doi.org/10.1109/DDECS.2008.4538806
Publication status	Published - 2008
Event	2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS - Bratislava, Slovakia Duration: 16 Apr 2008 → 18 Apr 2008

Conference

Conference	2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
Country/Territory	Slovakia
City	Bratislava
Period	16/04/08 → 18/04/08

ASJC Scopus subject areas

Electrical and Electronic Engineering
Control and Systems Engineering

Access to Document

10.1109/DDECS.2008.4538806

Cite this

@conference{b3bf9c7814b74880b3179e256553a537,

title = "The influence of global parametric faults on analogue electronic circuits time domain response features",

abstract = "This paper presents an analysis of an influence of global parametric faults (GPF) on analogue integrated circuits (AIC) time domain (TD) response features, such as overshoot, delay time, rise time, maxima and minima, first differential maxima and minima. The novel approach is the analysis of relations and superrelations between features which are discussed in details. The presented results should increase testability and diagnosability of the global parametric faults on a production line of analogue and mixed electronic circuits. The recently observed AIC faults belong to parametric ones and are caused by technological process. GPF influence on aforementioned features is presented with the use of an exemplary circuit. A research presented in this paper may be used as an introduction to a Fault Driven Test (FDT) diagnosis with the use of Simulation Before Test (SBT) methods.",

author = "P. Jantos and D. Grzechca and T. Golonek and J. Rutkowski",

year = "2008",

doi = "10.1109/DDECS.2008.4538806",

language = "English",

pages = "299--303",

note = "2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS ; Conference date: 16-04-2008 Through 18-04-2008",

}

TY - CONF

T1 - The influence of global parametric faults on analogue electronic circuits time domain response features

AU - Jantos, P.

AU - Grzechca, D.

AU - Golonek, T.

AU - Rutkowski, J.

PY - 2008

Y1 - 2008

N2 - This paper presents an analysis of an influence of global parametric faults (GPF) on analogue integrated circuits (AIC) time domain (TD) response features, such as overshoot, delay time, rise time, maxima and minima, first differential maxima and minima. The novel approach is the analysis of relations and superrelations between features which are discussed in details. The presented results should increase testability and diagnosability of the global parametric faults on a production line of analogue and mixed electronic circuits. The recently observed AIC faults belong to parametric ones and are caused by technological process. GPF influence on aforementioned features is presented with the use of an exemplary circuit. A research presented in this paper may be used as an introduction to a Fault Driven Test (FDT) diagnosis with the use of Simulation Before Test (SBT) methods.

AB - This paper presents an analysis of an influence of global parametric faults (GPF) on analogue integrated circuits (AIC) time domain (TD) response features, such as overshoot, delay time, rise time, maxima and minima, first differential maxima and minima. The novel approach is the analysis of relations and superrelations between features which are discussed in details. The presented results should increase testability and diagnosability of the global parametric faults on a production line of analogue and mixed electronic circuits. The recently observed AIC faults belong to parametric ones and are caused by technological process. GPF influence on aforementioned features is presented with the use of an exemplary circuit. A research presented in this paper may be used as an introduction to a Fault Driven Test (FDT) diagnosis with the use of Simulation Before Test (SBT) methods.

UR - https://www.scopus.com/pages/publications/50649093557

U2 - 10.1109/DDECS.2008.4538806

DO - 10.1109/DDECS.2008.4538806

M3 - Paper

AN - SCOPUS:50649093557

SP - 299

EP - 303

T2 - 2008 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Y2 - 16 April 2008 through 18 April 2008

ER -

The influence of global parametric faults on analogue electronic circuits time domain response features

Abstract

Conference

ASJC Scopus subject areas

Access to Document

Other files and links

Fingerprint

Cite this