Porting wire-grid MoM framework to reconfigurable computing technology

Tomasz Topa

doi:10.1109/LAWP.2020.3012587

Porting wire-grid MoM framework to reconfigurable computing technology

Tomasz Topa

Department of Electronics; Electrical Engineering and Microelectronics (RAU/RAU11)

Research output: Contribution to journal › Article › peer-review

13 Citations (Scopus)

Abstract

In this letter, a CPU/field-programmable gate array (FPGA) coprocessing implementation of the matrix assembly phase of the method of moments (MoM) is presented. The approach combines the frequency-domain integral equation-based formulation with piecewise-linear (triangular) basis function and method of images to evaluate the radiation pattern of the localizer antenna system. To benefit from the given hardware architecture, the code executed on the device runs only one single work-item OpenCL kernel. Using the Nallatech 385 A device featuring one Intel Arria 10 FPGA, a speedup ratio of about 2.08× is reported when compared to the reference single-core CPU approach, and about 1.11× when compared to the two-core CPU implementation.

Original language	English
Article number	9151276
Pages (from-to)	1630-1633
Number of pages	4
Journal	IEEE Antennas and Wireless Propagation Letters
Volume	19
Issue number	9
DOIs	https://doi.org/10.1109/LAWP.2020.3012587
Publication status	Published - Sept 2020

Keywords

Field-programmable gate arrays (FPGA)
graphics processing unit (GPU)
method of images
method of moments (MoM)
pipeline parallelism

ASJC Scopus subject areas

Electrical and Electronic Engineering

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10.1109/LAWP.2020.3012587

Cite this

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abstract = "In this letter, a CPU/field-programmable gate array (FPGA) coprocessing implementation of the matrix assembly phase of the method of moments (MoM) is presented. The approach combines the frequency-domain integral equation-based formulation with piecewise-linear (triangular) basis function and method of images to evaluate the radiation pattern of the localizer antenna system. To benefit from the given hardware architecture, the code executed on the device runs only one single work-item OpenCL kernel. Using the Nallatech 385 A device featuring one Intel Arria 10 FPGA, a speedup ratio of about 2.08× is reported when compared to the reference single-core CPU approach, and about 1.11× when compared to the two-core CPU implementation.",

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Porting wire-grid MoM framework to reconfigurable computing technology

Abstract

Keywords

ASJC Scopus subject areas

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