Abstract
The paper presents a complete approach to the multithreaded execution of a control program prepared according to IEC61131-3 standard. The program is mapped to a dedicated multiple-core CPU unit. The CPU consists of multiple independent bit and word CPUs. The computation synchronization mechanism is based on memory cells with semaphored access, which enable hardware-level synchronization. The paper presents in detail the architecture, results of implementation and the achieved performance. The custom-developed compiler translates standard programming languages into a multithreaded executable form. It utilizes an original intermediate data flow graph to optimize and recognize program parallelisms. The program is automatically partitioned and mapped to the available computing resources. The paper is concluded with a performance comparison of program executions using the standard single-threaded and proposed approaches.
| Original language | English |
|---|---|
| Article number | 1850162 |
| Journal | Journal of Circuits, Systems and Computers |
| Volume | 27 |
| Issue number | 10 |
| DOIs | |
| Publication status | Published - 1 Sept 2018 |
Keywords
- FPGA
- IL
- LD
- PLC
- SFC
- compiler
- control program optimization
- data flow graph
- multiple-core CPU
- parallel computation
- programming
ASJC Scopus subject areas
- Hardware and Architecture
- Electrical and Electronic Engineering
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