@inproceedings{2ae58b6ac50847358b336b05a959142d,
title = "Hardware implementation of the MD5 algorithm",
abstract = "The paper presents a hardware implementation of the MD5 hash generator. The generator comprises MD5 processing unit, data exchange interface and memory block for storing input messages. A general concept and implementation of the MD5 generator modules is described. Presented solution is based on the finite state machines; its performance is compared with other MD5 implementations. The MD5 generator has been modelled using VHDL and targeted to a Xilinx Spartan-3E device. Unlike compared implementations, which are mainly designated for Internet applications, this module is optimised to work as a part of video based device for measuring road traffic parameters. The MD5 generator is responsible for signing video stream captured in real time.",
keywords = "Cryptography, FPGA, Hash functions, MD5",
author = "D. Pamula and A. Ziebinski",
year = "2009",
doi = "10.3182/20090210-3-cz-4002.00012",
language = "English",
isbn = "9783902661418",
series = "IFAC Proceedings Volumes (IFAC-PapersOnline)",
publisher = "IFAC Secretariat",
number = "1 PART 1",
pages = "45--50",
booktitle = "9th IFAC Workshop on Programmable Devices and Embedded Systems, PDES 2009 - Proceedings",
edition = "1 PART 1",
}