Abstract
The paper presents an original method of implementing control programs, represented in Ladder Diagram (LD) format, in Programmable Logic Devices. The essence of the solution proposed in the paper consists in an original algorithm of extracting events that have to be processed sequentially, or can be processed concurrently. For this purpose a Network Ordered Graph is used. The graph is a link between a control algorithm described in Ladder Diagram, and the same algorithm described in Hardware Description Language (HDL).
| Translated title of the contribution | Sprzętowa realizacja programu sterowania w strukturach FPGA |
|---|---|
| Original language | English |
| Pages (from-to) | 95-100 |
| Number of pages | 6 |
| Journal | Przeglad Elektrotechniczny |
| Volume | 88 |
| Issue number | 12 A |
| Publication status | Published - 2012 |
Keywords
- FPGA
- Hardware control program realisation
- Ladder diagram
- Programmable logic controller
- Programmable logic device
ASJC Scopus subject areas
- Electrical and Electronic Engineering
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