FPGA support in hybrid simulation using finite element method

Hybrid simulation, or hybrid testing, is understood here as a numerical technique for investigating dynamic properties of mechanical systems with components that are difficult to model numerically. This technique can be also referred to as hardware-in-the-loop simulation. The idea of hybrid simulation is that the non-linear part of the system that is difficult to model numerically is tested experimentally and the rest of the system is modeled numerically. Therefore two models are created – the experimental model and the analytical model. During the simulation both models are in strict cooperation in order to act like the undivided system. The following paper focuses on utilizing FPGA (field-programmable gate array) in the computations performed in the analytical model. FPGA is an integrated circuit that is configured by the user. Physically FPGA is an array of logic blocks that the user can program and reconfigure interconnects that will allow to connect logic blocks in the desired way in order to perform complex functions. The most important advantages of using FPGA are flexibility, highly parallel data processing (thanks to simultaneous operation of independent circuits), high efficiency and reliability. Therefore complex digital computations that are implemented to FPGA can be executed with great speed. In the presented research the non-experimental part of the mechanical system is modeled using Finite Element Method (FEM). In order to control the experimental model in a closed loop, the FEM computations must be performed in real time. As FEM is computationally demanding method, the computations must be conducted as efficiently as possible in order to enable real-time without losing accuracy. The following paper describes increasing the time performance of the hybrid simulation algorithm by executing it on the microprocessor of a microcontroller equipped with real-time operating system while performing the most computationally demanding operations on the FPGA.