@inproceedings{08d12a3aa658418da877ee1b6fbe0039,
title = "Central processing units for PLC implementation in Virtex-4 FPGA",
abstract = "The paper presents an approach to the design and construction of central processing units for programmable logic controllers implemented in a FPGA development platform. Presented units are optimised for minimum response- and throughput time. The CPU structure is based on bit-word architecture and two types of control data exchange methods: with handshaking - control data are passed through the two flip-flop units with acknowledgement; without handshaking - control data are passed through the dual port RAM. Third unit - simple one processor - built to compare with the above two. The paper presents specific timers/counters hardware construction solution. Additionally it presents implementation results which show how many FPGA circuit resources are used to implement presented units.",
keywords = "Central processing unit, Concurrent programs, Field programmable logic array (FPGA), Programmable logic controller (PLC), Throughput time",
author = "M. Chmiel and J. Mocha and E. Hrynkiewicz and A. Milik",
year = "2011",
doi = "10.3182/20110828-6-IT-1002.01830",
language = "English",
isbn = "9783902661937",
series = "IFAC Proceedings Volumes (IFAC-PapersOnline)",
publisher = "IFAC Secretariat",
number = "1 PART 1",
pages = "7860--7865",
booktitle = "Proceedings of the 18th IFAC World Congress",
edition = "1 PART 1",
}